Modern processors operate under a very low voltage and a high current to meet the demands for faster and more efficient data processing. The voltage regulator module (VRM) must be used to provide power for the microprocessors.
Please refer to FIG. 1, there is depicted an interleaved synchronous buck topology with at least two interleaving channels that is widely used in 5V/12V input VRM. The phase difference between each adjacent interleaving channel is 360 degree divided by the number of channels interleaved.
FIG. 2 shows a basic cell for interleaved synchronous buck converter shown in FIG. 1. A DC voltage input Vin at an input capacitor 210 is connected to the output lead 211 through a rectifier circuit 201, shunted by output capacitance 212. The rectifier circuit 201 contains a high side MOSFET 213, a low side MOSFET 215 and a magnetic device 214 as an output inductor. The drain of low side MOSFET 215 is connected by the source electrode of the high side MOSFET 213 and an input terminal 216 of an inductor 214 to support a freewheeling current. When the high side MOSFET 213 turns on and the low side MOSFET 215 turns off, there will be a high level on the terminal 216 and the current will support a load through the high side MOSFET 213 and the inductor 214. When the high side MOSFET 213 turns off and the low side MOSFET 215 turns on, there will be a low level on the input terminal 216 and the current will be freewheeled through the low side MOSFET 215 and the inductor 214. Therefore, there will be a square waveform voltage on the input terminal 216 of output inductor 214.
In general, the input voltage for most VRMs is 5V or 12V, and the output voltage is lower than 3.3V. An interleaved synchronous buck converter and other improved structures are widely used. A single channel buck converter includes buck switches and an inductor. Buck switches contain a high side MOSFET for conducting a load current from input during the first internal of a conduction/nonconduction period and a low side MOSFET for freewheeling the load current during the second interval other than the first interval. With the current ripple cancel effect, the interleaving technique can reduce the size of both input and output filter and improve the converter's transient response. Therefore, the interleaved buck converter is used to deal with a high current and high slew rate application.
However, the high input current in 12V or 5V input VRM will cause high power loss on the input power bus, and a large input filter is also needed for the increasing transient demand. Therefore, 48V input bus is proposed as alternative to reduce the input current and power bus loss, also to reduce the size of input filter.
Isolation is needed for a 48V input VRM. A basic solution for 48V input VRM is applying two-stage approach in which 48V voltage firstly is transferred to a lower DC voltage by a DC/DC converter, and then an interleaved synchronous buck converter finishes the post energy conversion. But this scheme has too big size because too many semiconductors and at least two magnetic devices should be used. So it aggravates the design and application for 48V input VRM seriously.
For 48V input VRM shown in FIG. 3 illustrates a conventional two-stages VRM schematic of prior art with a front half-bridge converter 304 transferring 48V to a low DC voltage and a post interleaved synchronous buck 302 converter finishing the second-step voltage conversion. Apparently this scheme has one more front converter than 12V VRM topology. So it needs more semiconductors, magnetic devices and other passive devices. The control is also complex because two controllers should be used. Generally, this scheme increases the VRM's cost, profile and complicity for productivity.
Accordingly, what is needed in the art is a new structure which can simplify the VRM design. More particularly, it will be very abstractive if this structure is similar to the buck topology. It is therefore attempted by the applicant to deal with the above situation encountered with the prior art.